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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 5-19. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory (1)(2)
Figure 5-20 , and Figure 5-21 ) (continued)
CV DD = 1.3 V
(3) (4)
(see Figure 5-18 ,
NO.
PARAMETER
MIN
DV DDEMIF = 3.3/2.75/2.5/1.8 V
NOM
MAX
UNIT
22
23
24
25
t w(EMWEL)
t d(EMWAITH-EMWEH)
t su(EMDV-EMWEL)
t h(EMWEH-EMDIV)
EM_WE active low width (EW = 0)
EM_WE active low width (EW = 1)
Delay time from EM_WAITx deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
(WST)*E - 7.5
(WST+(EWC*16))*E - 7.5
3E - 7.5
(WS)*E - 7.5
(WH)*E - 7.5
(WST)*E
(WST+(EWC*16))*E
4E
(WS)*E
(WH)*E
(WST)*E + 7.5
(WST+(EWC*16))*E + 7.5
4E + 7.5
(WS)*E + 7.5
(WH)*E + 7.5
ns
ns
ns
ns
ns
BASIC mSDRAM
1
EM_SDCLK
EM_CS[1:0]
EM_DQM[1:0]
EM_BA[1:0]
WRITE OPERATION
3
5
7
7
2
3
7
7
2
5
EM_A[20:0]
9
9
EM_D[15:0]
11
11
EM_SDRAS
13
EM_SDCAS
15
15
EM_WE
Figure 5-16. EMIF Basic SDRAM/mSDRAM Write Operation
Copyright ? 2010–2013, Texas Instruments Incorporated
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